FIG. 1 illustrates a typical Synchronous Dynamic Random Access Memory (SDRAM) 10, which could include for example a Double Date Rate (DDRx) SDRAM. Specifically shown is a data bus 11 by which data enters and exits the chip. As is typical, this data bus 11 comprises several signals DQ1-DQn which operate in parallel. As is common in SDRAMs, such data is accompanied by a data strobe signal (DQS) which, generally speaking, informs as to the times at which the data can be considered valid. The use of a data strobe signal thus helps to synchronize the data to and from the SDRAM 10.
In some architectures, such as DDR2 or DDR3, the data strobe signal is differential. This means the data strobe (DQS) is always provided with its complement (DQS*), and as such FIG. 1 illustrates two connections on the SDRAM 10 for such complementary signals. As one skilled in the art will appreciate, use of a differential signal improves the overall signal integrity of the data strobe signal.
Also evident in FIG. 1 are external power supply connections to the SDRAM 10. Specifically shown are two sets of power supply voltages: Vdd and Vss; and Vddq and Vssq. Each set is isolated from the other: Vdd is isolated within the SDRAM 10 from Vddq, and likewise for Vss and Vssq. As one skilled in the art will recognize, Vdd and Vddq typically comprises a positive voltage (perhaps 1.5V or so; Vdd and Vddq can however differ from one another), while Vss and Vssq comprise a lower potential which is usually ground (i.e., 0V; again, they can differ). An actual SDRAM 10 would of course have other inputs and outputs as well (e.g., address and control signals), but these are not shown in FIG. 1 because such other signals are not of particular relevance to the subjects discussed herein.
Isolation of the power supply sets allows for each set to power different circuitry blocks within the SDRAM 10. Typically, the Vdd/Vss power supply set powers most of the normal logic circuitry in SDRAM 10, such as the array, decode/driver circuitry, and associated logic. By contrast, the Vddq/Vssq power supply set powers the output driver circuitry 20 at least in part, as shown in FIG. 2. Shown in FIG. 2 are the output paths for the differential data strobe signal (both DQS and DQS*) and the various data output signals (DQ1-DQn), which signals typically terminate at bond pads 13 on the SDRAM 10.
As can be seen, in each of these output paths, up (UP) and down (DN) drive signals are used to drive the bond pads 13 to a particular logic level. When the output paths are outputting signals to the pads 13, the UP and DN drive signals will (in the illustrated example) be the same in a given path. Therefore, to drive DQS high, UP(s)=DN(s)=logic ‘1.’ To drive DQS low, UP(s)=DN(s)=logic ‘0.’ The drive signals UP(s) and DN(s) could however be complementary in other configurations.
(Even though the UP and DN drive signals are disclosed herein as being tied to the same logic level, one skilled in the art will understand that it can still be useful to have these drive signals split so that each can be independently controlled during times when an output is not being driven to the pads 13. For example, independent assertion of UP and DN can be useful during times when the pad is receiving signals to set a proper termination resistance. For further details, see Micron Technical Note DDR3 ZQ Calibration (2008) (http://download.micron.com/pdf/technotes/DDR3/TN4102.pdf), which is submitted in an Information Disclosure Statement filed with this application).
Complements of the drive signals (UP(s)*/DN(s)*) are used to drive DQS* to complementary logic levels. Therefore, to drive DQS* high, UP(s)*=DN(s)*=logic ‘1.’ To drive DQS* low, UP(s)*=DN(s)*=logic ‘0.’
Because each of the output signals are transferred off of the SDRAM 10, where they will encounter higher capacitances presented by a printed circuit board for example, it is generally preferred to boost the power of the drive signals to ultimately boost the power of the signals generated at the pads 13. Accordingly, each of the drive signals is progressively boosted along their output paths to higher power capacities by a series of stages. In FIG. 2, stages a-e comprise serially-connected CMOS inverters 14, with stages f merely comprising serially-connected pull-up or pull-down transistors. Other types of stages can be used as well. In each successive stage, larger (or wider) transistors are used to increase output current. Thus stage b is larger than stage a; stage c is larger than stage b, etc.
Successive boosting of the power of the drive signals raises the risk of corrupting of the power supply voltages by noise. Accordingly, it is preferred, as shown in FIG. 2, to use two isolated power supply sets, such as the Vdd/Vss and Vddq/Vssq sets. These power supply sets may be unregulated by the SDRAM 10, such that they comprise the externally-asserted supplies discussed earlier with respect to FIG. 1. Or, they may comprise versions of these external supplies internally regulated by the SDRAM 10. In any event, the sets are shown in FIG. 2 and in subsequent figures using the same Vdd/Vss and Vddq/Vssq nomenclature for simplicity, which may comprise either regulated or unregulated supplies.
As shown, the first two stages a and b in the output driver circuitry 20 are powered by the Vdd/Vss power supply set. As mentioned earlier, such power supply set may be used to power the array and logic circuitry in the SDRAM 10. The last stages c-f in the output driver circuitry 20 are powered from the Vddq/Vssq power supply set, which is usually dedicated to the output driving task. Through this use of dual power supply sets, noise present on the Vddq/Vssq power supply set, as might result from the high-current switching of data at the later stages in the output paths, should not be transferred to the Vdd/Vss power supply set feeding the remainder of the circuitry on the SDRAM 10.
This dual power supply set scheme means that the drive signals must pass from one power supply domain (i.e., the Vdd/Vss domain) to another power supply domain (i.e., the Vddq/Vssq domain), which boundary occurs at the dotted line 15 between stages b and c in the example illustrated in FIG. 2.
While the transition of the drive signals between these power supply domains helps to isolate noise between the domains, the decoupling of these two power supply domains has drawbacks. In particular, decoupling the Vddq/Vssq domain from the Vdd/Vss domain renders the Vddq/Vssq domain more susceptible to switching noise than it would be were the entire SDRAM 10 governed by a single, more-heavily-loaded, power domain. As a result, the absolute levels for Vddq/Vssq can more readily shift to higher or lower values in response to such switching noise. Such noise can be heavily dependent on the particular logic levels being output at the bond pads 13 at a given time. For example, the output of all logic ‘1’s on DQ<1:n> creates a particularly power-intensive situations which might load down Vddq, while the output of all logic ‘0’ on DQ<1:n> might similarly increase Vssq. Given the high capacitance between Vddq and Vssq, deviations in one of these power supply voltages will similarly affect the other, such that Vddq and Vssq will tend to vary together while maintaining a constant difference between them. For example, if Vddq ideally equals 1.5V and Vssq ideally equals 0V, noise may cause Vddq to equal 1.4V thus causing Vssq to equal −0.1V. Or, noise may cause Vssq to equal 0.1V thus causing Vddq to equal 1.6 Volts.
It has been noticed by the inventor that such noise-induced perturbations to the Vddq/Vssq power domain relative to the Vdd/Vss power domain have unfortunate effects for the operation of SDRAM 10, and in particular for the integrity of the differential data strobe signal. In particular, it has been noticed that variations in Vddq and Vssq has a negative effect on a particular specification for the differential data strobe signal, referred to as Vox. Fortunately, the inventor has also developed a solution to this problem, as set forth below.